Power semiconductor devices are used today in a wide range of electronic systems including power supplies, voltage regulators, DC/DC converters, motor drives, safety switches, battery disconnect switches, power-saving load switches, current limiters, port protection devices, audio amplifiers and more.
In many, if not most, power electronic applications, current sensing is important both for circuit operation and for safety and protection features. While the requirement for current sensing varies, for applications drawing more than 300 mA, the need for current sensing is common. The most common use for monitoring current is in an over-current shutdown or OCSD function. The purpose of OCSD is to shut off the circuit if large and potentially dangerous currents begin to flow.
A common condition leading to an over-current condition occurs when a load is shorted. For this reason, OCSD is often referred to as “short circuit” or “crowbar” protection. Various approaches exist for the location where the current is monitored, i.e. in the load, or in the transistors controlling the load. Oftentimes access to a location directly in the path of the load is not practical so that current monitoring is instead performed in an active device, transistor, or semiconductor component, and preferably in a device controlling the current flow into the circuit from its power input or source, e.g. a generator, battery, or regulated power supply.
Another approach to monitoring current is to facilitate current-limiting. In power devices such as power MOSFETs or IGBTs, where the drain current saturates, using feedback the device can be operated such that its drain current remains relatively constant regardless of its drain-to-source voltage. Since voltage is sustained while current is conducted, the current-limiter uses power according to the equation Ploss=VDS·ID. In the event the product of ID and VDS becomes too large for a sustained time interval, the device will overheat and may be damaged. Current-limiting therefore is often coupled with over-temperature protection circuitry that shuts an overheating device off before irreparable damage occurs to the device or the system. Nonetheless, accurate current limiting demands accurate measurement of a device's current.
In other applications, current information is used in system control. For example, in current-mode switching power supplies, load current information is used to control the slope of a voltage ramp fed into the error amplifier, thereby affecting regulation quality, transient response time, and circuit stability. In slew-rate controlled load switches the current is ramped under closed-loop control to minimize noise and transient current spikes. Using current feedback, often in conjunction with voltage feedback, closed-loop control improves both system controllability and stability.
Conventional Current Sensing Techniques:
Four techniques are commonly employed for current sensing. These prior art methods comprise                Current sense resistors        VDS sensing        Magnetic current sensing        Integrated current mirrors        
These sensing techniques, their principles of operation, circuit implementation, and electrical characteristics are described herein.
The most general purpose current sensing technique employs a current sensing resistor. Shown in FIG. 1A, current sense circuit 1 includes a push-pull power output stage comprising a P-channel MOSFET 4 and an N-channel MOSFET 3 driving a load or inductor 9. A current sense resistor 2 of resistance Rsense is inserted between the Vcc power input and the source of P-channel MOSFET 4 to sense the current flowing into the circuit. An operational amplifier 5 boosts the signal, i.e. the voltage, measured across sense resistor 2. The voltage Vo on the output of amplifier 5 is proportional to the current I in sense resistor 2, as given by the relationVo=Av(I·Rsense+Voffset)∝I where Av is the closed loop voltage gain of amplifier 5 and Voffset is any voltage offset present in the amplifier, either positive or negative in polarity. The resistive current sense circuit delivers the signal Vo to control circuitry which may include analog circuitry such as PWM control, slew rate control, current limiting, etc.
The voltage Vo may also be used to make no/no-go decisions like over current shutdown using a comparator 6 and a voltage reference 7. Whenever the current in MOSFET 4 exceeds some pre-specified value, the output of comparator 6 reacts and flips its state, signaling that an over-current condition has occurred. Comparator 6 often includes hysteresis to avoid chattering, i.e. unwanted oscillation, around the comparator's trip point.
Benefits of the sense resistor approach include its ability to measure both the current in a MOSFET and its parasitic source-to-drain diode, whenever it conducts. If a zero temperature coefficient resistor is used, the current measurement can be made accurately over a wide range of temperatures. It may be used in conjunction with any device either integrated or discrete with the caveat that parasitic inductance between the resistor and the semiconductor must be kept small by careful layout of the printed circuit board.
Unlike other current sensing techniques, the sense resistor method can measure current in any of the operating regions of a device, whether it is acting as a switch or as a current source. For example, a sense resistor can measure current in a MOSFET operating in its linear region, i.e. acting as a variable resistor. It can also measure current in a MOSFET operating in its saturated region of operation, i.e. acting as constant current source or current limiter. The method can even measure MOSFET current in the edge-of-saturation transition or so-called “knee” region between the linear and saturation regions. It can also measure current when the device is in avalanche breakdown.
Moreover, independent of the value of Vcc, no high voltage ever appears across sense resistor 2, so the input to amplifier 5 need not survive high voltages or use high voltage devices. Connected to the source of MOSFET 4, the maximum voltage possible across resistor 2 is limited in magnitude to an amount equal to |VGS−Vt|, where as shown VGS is the gate voltage on P-channel MOSFET 4 with respect to its source and Vt is threshold voltage of P-channel MOSFET 4. So, for example, if VGS=−5V, then for a −1V threshold voltage the maximum voltage across resistor 2 and on the input of amplifier 5 is limited to 4V even if Vcc=24V.
Another benefit of using a sense resistor is that if a discrete sense resistor is employed, the accuracy of the resistor can be specified to a tolerance of ±1% or ±0.5% as needed. The accuracy of the sense circuit is then limited by the offset voltage of amplifier 5, provided that the measured signal is large compared to the amplifier's input offset voltage. It is not always reasonable to assume that assumption is valid.
The problem with the sense resistor current sensing method is an intrinsic and unavoidable compromise between noise, i.e. signal-to-noise, and unwanted power loss. If the resistance Rsense of sense resistor 2 is too small, the voltage measured across it will be extremely sensitive to noise and difficult to measure. Since the voltage is being measured in the device's main current path, transients, current spikes, and capacitive displacement currents appear instantly as a signal on the input of amplifier 5, causing a noisy and jittery output.
Conversely, if the value Rsense is too large, excessive I2·Rsense power dissipation will occur in resistor 2, degrading efficiency and leading to unwanted die heating. For example, if the resistance of the sense resistor 2 is chosen to be 10% that of series connected MOSFET 4, then for a MOSFET with an on-resistance of 150 mΩ, the value of Rsense must be 15 m≠. At a 2 A load current in steady state, MOSFET 4 will dissipate 0.6 W, and sense resistor 2 will dissipate 10% of that amount or another 60 mW. Ignoring any switching losses, together the resistor and MOSFET will dissipate 660 mW. The voltage Vsense across resistor 2 is then given by Vsense=I·Rsense or 300 mV, a value easy to integrate, measure and use in active control circuitry.
If on the other hand power MOSFET 4 has a resistance of 20 mΩ to improve efficiency by reducing conduction losses, then a 10% current sense resistor has a value of only 2 mΩ and at 2 A exhibits only 4 mV drop, smaller than the offset voltage of smaller amplifiers. The accuracy of such a circuit will be very poor, since variations in the offset voltage of amplifier 5 can vary by several milli-volts from one wafer lot to another.
To minimize this sensitivity, a 5 mΩ resistor exhibits a more measurable 10 mV drop across resistor 2, but unfortunately represents a 50% increase in power dissipation beyond the MOSFET's losses, meaning the total loss increases from 80 mW without the sense resistor to 100 mW, an overall increase of 25%. Also, as the magnitude of the offset and the measured value approach one another, i.e. as Vsense→Voffset, the current sense accuracy becomes very poor and can vary by 30% or more, even if a more expensive precision current sense resistor is used.
Another possible compromise is to increase the size of MOSFET 4 to lower its resistance to compensate for the extra resistance contributed by series sense resistor 2. This approach can help to some degree, but it is limited in switching circuits because any increase in the size of MOSFET 4 increases its capacitance and this causes a corresponding increase in switching losses. Such a tradeoff reduces conduction losses at the expense of increasing switching losses, particularly at higher switching frequencies.
An alternative to the current sensing resistor technique is VDS sensing. In VDS sensing, the voltage drop across the power MOSFET is used to calculate the current in the device. This measurement method is only valid when the MOSFET is operating in its linear region, i.e. behaving as an on-state switch with a semi-constant resistance. As shown in circuit 10 in FIG. 1B, the technique involves monitoring the voltage across a power MOSFET 12 with an operational amplifier 14 connected directly across the drain and source terminals of MOSFET 12. If MOSFET 12 is biased in its on state to be fully-enhanced, e.g. with VGS=−10V, then with an on-resistance RDS(on) the voltage output Vo of current sensing amplifier 14 is given byVo=Av(I·RDS(on)+Voffset)∝I where Av is the closed-loop voltage gain of amplifier 14 and Voffset is any voltage offset present in the amplifier, either positive or negative in polarity. The resistive current sense circuit delivers the signal Vo to control circuitry which may include analog circuitry such as PWM control, slew rate control, current limiting etc.
The voltage Vo may also be used to make no/no-go decisions such as over-current shutdown using a comparator 16 and a voltage reference 15. As designed, whenever the current in MOSFET 12 exceeds some pre-specified value, the output of comparator 16 reacts and flips its state, signaling that an over-current condition has occurred. Comparator 16 often includes hysteresis to avoid chattering, i.e. unwanted oscillation, around the comparator's trip point.
The advantage of VDS sensing is the function is virtually free, since it relies on measuring the voltage across power MOSFET 12, which may be an integrated or discrete MOSFET.
As long as the device being monitored for current is a MOSFET, the VDS sensing technique is applicable. Aside from the amplifier required to measure the value of VDS, there is no need for special bias circuitry or floating power supplies.
Unlike the current sensing resistor technique, since no additional devices are introduced in series with the high current path, VDS sensing can be considered a parallel monitoring technique. With no added series elements, there is no degradation in the power MOSFET's performance, and no increase in conduction losses or switching losses. The performance of the circuit is therefore identical to the performance of the device alone. Efficiency scales with voltage the same as in the device without current sensing.
One major problem with VDS sensing is it relies on the resistance of the power MOSFET to determine the current. Unfortunately, the resistance of a power MOSFET is sensitive to a myriad of electrical and process related parameters. In operation, dynamic and constant variations in VGS, VDS and temperature conditions all affect a MOSFET's resistance and disturb the circuit's ability to accurately detect current. These environmental influences cannot be simply cancelled using predictive or algorithmic approaches since process parameters such as threshold voltage Vt, epitaxial thickness and doping, junction depths and concentrations, and even metal thickness and bond wire placement affect the linear region ID−VDS characteristics of a power MOSFET.
For a specific device for example, electrical bias and thermal ambient conditions can easily result in a ±25% variation in current, especially if a high value of VDS pushes the device into quasi-saturation, i.e. in the knee region between the linear and saturated operating regions. Including batch-to-batch process variations, current sensing tolerance could be as bad as ±50%. A change in packaging, vendor, wafer fab, or heat sinking could cause the VDS sensing and over-current protection circuitry to fail altogether. In some instances, system designers have been known to intentionally change the size and on-resistance of a power MOSFET in an application not realizing they inadvertently disabled operation of the over-current protection.
Since VDS sensing relies on a device behaving as a semi-constant resistance, it cannot be used to detect current in IGBT's, thyristors, diodes or any device that includes minority carrier transport or conductivity modulation, since such devices do not manifest a linear voltage-current relationship. VDS sensing also cannot monitor diode current in a power MOSFET and does not detect avalanche current.
Another complication of using VDS sensing is that operational amplifier 14 is subjected to the same voltages, voltage transients and spikes as power MOSFET 12 and must be able to survive these voltages without damage. Even more complex, the operation of the VDS over-current detection circuitry must be disabled whenever MOSFET 12 is turned off or undergoing a switching transient, e.g. when the device is conducting current while VDS is momentarily large.
Since the output of over-current comparator 16 is valid only when MOSFET 12 is fully on and its resistive state, any controller using VDS sensing must “blank”, i.e. ignore, the over-current detect flag during all other times. If a short circuit occurs while the VDS detect circuit is disabled, the circuit is unprotected from damaging and potentially dangerous over-current conditions. In order not to rely solely on VDS sensing, additional circuitry must be included to check for these various fault scenarios.
Magnetic current sensing, another current sensing technique, relies on time varying electric currents to induce a magnetic field and measures the magnetic field strength to calculate the current in accordance with Maxwell's equations. To accurately measure the field, the magnetic sensor must fully surround the conductor. Device dimensions in integrated circuits and most components are too small to generate substantial magnetic fields.
Detection sensitivity is equally problematic, since other causes may disturb the magnetic sensor and give false readings. Finally, most magnetic detection systems have a fairly low bandwidth and are incapable or reacting to the microsecond changes common in electrical systems and voltage regulators. Magnetic sensing is therefore not a viable option for current sensing in the majority of power electronic systems.
Split-Drain MOSFET with Integrated Current Sensing;
The most common current-sensing technique in power integrated circuits is the split-drain current mirror 20, illustrated in FIG. 2A. A high-side current mirror 22 comprises two planar MOSFETs 23A and 23B, one large, one small, having common source and gate terminals. The smaller MOSFET 23B, with a gate width W, carries a current I2 set by a dependent current source 24. The current I2 is generally adjusted in response to feedback signal 27 regarding the voltage VD1 on the drain of the main power MOSFET. The larger main power MOSFET 23A, with a gate width “n” times W, is connected to a load 21 and to a low-side MOSFET 25. MOSFETs 23A and 25 together form a complementary MOSFET push-pull output driving load 21, and as such have comparable current ratings, e.g. where current I1 is two amperes or more.
The sense MOSFET 23B is ideally made as small as possible without sacrificing current sensing accuracy. The size ratio “n” commonly ranges over several orders-of-magnitude, from 10 to as high as a 106 or more, depending on various design considerations. For power electronic applications, the current sensor MOSFET 23B is generally at least three to four orders of magnitude smaller than the main power MOSFET 23A. Accordingly, under comparable bias conditions, the respective currents in the two MOSFETs of mirror 22 will be in a ratio proportional to the scale factor “n”, or
      I    2    =            I      1        n  
For example if n=5000, then ideally the size of the current I2 flowing in MOSFET 23B should be 0.05% of the size of the current I1 flowing in the main power MOSFET 23A. At this ratio, a one ampere load current will result in a 500 μA sense current I2. If n=10,000, sense current I2 is reduced to 10 μA. Currents below one microampere are more noise sensitive and ill advised.
The key aspect in implementing current mirror 22 is to design the sense MOSFET 23B in an identical construction to the main power MOSFET 23A and to co-fabricate the two devices in a common silicon dice. Monolithic co-fabrication minimizes the risk of batch-to-batch variations affecting matching, while mask design and device layout eliminate geometric related mismatch.
For example, FIG. 2B illustrates a current mirror pair of MOSFETs 30 comprising an active area 31 of width W containing a P+ source 34B and a P+ drain 35B, and further comprising an active area 32 of width n·W containing a P+ source 34A and a P+ drain 35A, where the source and drain implants are self aligned to a polysilicon gate 33 transecting active areas 31 and 32. The directional orientation of gate 33 is identical for both devices to improve matching and reduce any directional effects resulting from the fabrication process.
Source regions 34A and 34B are contacted with contacts 37A and 37B and share a common source metal interconnect 40B, which is connected to Vcc. P+ drain 35A is contacted with a contact 38A to a metal interconnect 40D, while P+ drain 35B is contacted with a contact 35B to a metal interconnect 40C. Gate 33 is connected through contact 39 and a metal interconnect 40A. While each of the devices is shown as a single stripe, the large device actually may comprise a number of parallel stripes of similar orientation to the smaller device.
In another example of a split-drain current mirror, a boost converter 41 in FIG. 2C includes an inductor 45, a rectifier 46, a capacitor 47 and an N-channel current mirror MOSFET pair 42 comprising a large MOSFET 43A with a load current I1 and a smaller sense MOSFET 43B carrying a sense current I2. Whenever VG1 is set to turn on the current mirror MOSFETs 43A and 43B, a dependent current source 44 adjusts the sense current I2 until the respective drain voltages of MOSFETs 43A and 43B are similar, i.e. VDS2≈VDS1.
One common way to force the two drain voltages to the same value is to employ an operational amplifier 48 to control the level of current I2 from current source 44. With one input tied to the drain voltage VD1 of power MOSFET 43A, and the other input tied to the drain voltage VD2 of current sensing MOSFET 43B, operational amplifier 48 will attempt to adjust the sense current I2 dynamically to drive the two voltages to the same value. The importance of dependent current source 44 to achieve accurate current sensing by normalizing the drain voltages VD2 and VD1 of sense MOSFET 43B and main MOSFET 43A depends heavily on the transistors' regions of operation.
As shown in FIG. 2D, graph 50 illustrates the ID−VDS current characteristics for the mirror MOSFETs 43A and 43B, with both MOSFETs biased at a fixed gate voltage VGS1. The curve representing the higher current I1 comprising regions 51A and 52A, represents the larger device, MOSFET 43A, having a gate width n·W. The curve representing the lower current I2 comprising lines 51B and 52B illustrates the smaller device, MOSFET 43B, having a gate width W. At any given value of VDS, the ratio of the currents I2/I1 is equal to n.
For example, in the saturated region of operation above VDS3, the condition of saturation VDS>(VGS1−Vt) is met by both curves 51A and 51B and drain current ID does not vary significantly with drain voltage. Specifically, at a drain voltage VDS4, the currents I1(sat) and I2(sat) at points 54A and 54B maintain a ratio of “n”, so that I2(sat)=n·I1(sat)
If the drain voltage on MOSFET 43B (point 54B) were shifted to VDS3, the current does not change substantially and the ratio “n” is still maintained despite a drain voltage mismatch. In other words, the importance of maintaining exactly the same drain voltage for current sensing in saturation is minimal. The role of dependent current source 44 is less important for drain voltages above VDS3. As shown in FIG. 2E, current sensing in saturation exhibits inaccuracies of ±15% as shown by curve 58 in graph 55, with the mismatch mostly due to device-related phenomena such as short channel effects.
Behavior of the current mirror when MOSFETs 43A and 43B are in their linear regions of operation is considerably different. Below a voltage VDS2, (VGS1−Vt)>VDS and the devices are both in their linear regions with currents 52A and 52B. Specifically, the currents 53A and 53B at a voltage VDS1 also exhibit a ratio of “n”, so that I2(lin)=n·I1(lin). Any slight deviation in VDS on the current sense device, i.e. where VD2≠VD1, results in a dramatic change in the current ratio and a significant error in measuring the current.
It follows that in the linear region accurate current measurement relies on dependent current source 44 maintaining the same drain voltage on both main MOSFET 43A and sense MOSFET 43B. Also shown by curve 56 in graph 55, in the linear region an accuracy of ±10% or better can be achieved, provided VDS is held constant for both devices. The slight improvement is because less process variables impact linear operation, and in particular linear region operation exhibits a lower sensitivity to threshold mismatch than operation in the saturation region.
In quasi-saturation, the region between the linear region and the saturation region, where VDS is between voltages VDS2 and VDS3, current mismatch is extremely sensitive to slight variations across a die in threshold, drain and source resistance, channel length modulation and stress induced piezoelectric effects. In quasi-saturation, the mismatch error (curve 57) increases, and can even be double the mismatch error observed in the linear region.
In conclusion, the split-drain MOSFET current mirror, comprising two conventional lateral MOSFETs of differing gate widths sharing a common gate and source connection can be used effectively as a current sensor in a low-voltage power device, either alone as a discrete current-sensing power MOSFET, or integrated into a power IC, e.g. into a low-voltage current limiter, battery charger, or PWM switching regulator IC.
Current sensing occurs in parallel to the main power device and does not require any series sense element inserted into the high current path that can degrade performance by increasing conduction or switching losses. As a mirror, many common-mode perturbations in its operation are cancelled out. The accuracy of the current mirror sensing technique and its related circuitry is therefore relatively immune to noise, changing load currents, supply voltage fluctuations, and to temperature variation. Implementation of a current-sensing power MOSFET using the split-drain current mirror technique involves minimal circuitry consuming low quiescent currents and does not require generating any floating supply voltages for circuit biasing.
The term “current mirror” is used throughout this disclosure in a broadly defined manner. According to a narrower definition, a MOSFET current mirror establishes its VGS gate bias using a threshold connected MOSFET where one device operates with a gate bias near its threshold voltage because it is hard-wired with its gate tied to its source, i.e. where VGS=VDS. A split-drain MOSFET pair is defined as a current mirror herein even though VGS is imposed on both devices from a gate buffer, not derived from the main device's drain current. A split-drain MOSFET pair behaves in a manner similar to a current mirror according to the narrower definition inasmuch as the current in one MOSFET is a scalar multiple of the current in the other MOSFET and common-mode noise that perturbs the drain current is cancelled out.
The split-drain current mirror offers superior current matching in its linear region of operation provided that the current-sense and main power MOSFETs are monolithically integrated using identical geometries and gate orientations, and in operation biased to the same VDS values. The split drain also offers moderately good current matching in saturation, i.e. as a current source, with the advantage that current matching accuracy in this region is relatively immune to VDS bias conditions, provided that the device is operated outside of its quasi-saturation “knee” region. In other words, when biased in saturation, the split-drain current mirror sense technique ignores variations in the drain voltage.
The split-drain current mirror power MOSFET can easily be fabricated as a low-voltage power device in a planar CMOS process by scaling the power MOSFET to very large gate widths, millions of microns in width, to reduce its on-state resistance. Fabrication in 0.5 micron, 0.35 micron and even 0.18 micron CMOS processes with thick multi-layer metallization yields devices with low specific on-resistance capable of blocking three to five volts in their off state. The devices utilize lateral current flow, parallel to a die's surface, under a planar gate located atop the silicon surface. Using such planar IC processes, five-volt MOSFETs with milliohm on-resistances have been demonstrated and commercialized. Being CMOS-compatible, the device can easily be integrated within monolithic PWM switching voltage regulators, smart switches and current limiter circuits, and integrated battery chargers.
Despite its numerous benefits, however, the split-drain current-mirror current sensing technique suffers from a number of significant deficiencies. One major disadvantage of this circuit is that the drain of the main power MOSFET, often the noisiest and highest voltage node in a system, must be monitored in order to control the current biasing the current sense MOSFET.
In FIG. 2C for example, operational amplifier 48, used to control current source 44, has its input connected to the V, node of a boost converter 41. If boost converter 41 is a high voltage circuit, operational amplifier 48 requires a high-voltage input rating in order to survive the entire range of voltages that occur at the V, node, including transients. Moreover, any voltage error in the operational amplifier due to input voltage offset is manifested as a current mismatch and an error in the circuit's ability to accurately measure current.
Another limitation of sensing current with a split-drain MOSFET current-mirror sensing technique is that it is unable to measure avalanche current or forward biased diode current. As a result, it cannot detect certain fault conditions that the sense resistor method of FIG. 1A can detect. The greatest limitation of the split drain MOSFET current sensor, however, is its technological specificity—it can only be fabricated in planar power devices, and planar MOSFETs suffer from many limitations.
Limitations of Planar Power MOSFETs:
Planar power MOSFETs comprise large gate width MOSFETs with top-side source and drain connections and a metal-oxide-semiconductor or “MOS” gate structure formed atop the silicon's planar surface. The devices may comprise N-channel or P-channel MOSFETs or the complementary combination thereof often referred to as CMOS. Despite their versatility, such devices suffer from numerous restrictions inherent in their construction. These limitations restrict the use of planar power MOSFETs in a variety of areas, including voltage scaling, reliability and circuit topology.
Voltage Scaling Limitations in Planar MOSFETs:
Lateral MOSFETs produced using a planar CMOS fabrication process have a limited voltage scalability. In a lateral MOSFET, a lightly-doped-drain extension, also known as an extended drain or drift region, is used to increase the avalanche breakdown voltage. In a high-voltage LDD device, the breakdown voltage increases linearly with drift length LD. The breakdown voltage BV increases about 10V to 12V for every micron of drift length, as measured by the critical electric field of avalanche Ecrit. Due to surface effects, the strength of this critical field at the wafer's surface is only one half of what it is in the silicon bulk. For long drift lengths, the breakdown voltage BV≈Ecrit·LD, or LD≈BV/(Ecrit), so that a 10 micron drift region breaks down at about 100V, at 20 micron drift region breaks down at about 200V and so on.
The transistor area efficiency, or packing density A/W, is significantly lower for lateral devices than vertical devices because the high-voltage drift region and both the drain and the source contacts are located on the die's surface. For a device having a striped surface geometry with a long drift, for example, a lateral high voltage MOSFET with a gate width W consumes an area of W·LD so that for every micron of gate width the device's packing density A/W≈LD. Increasing the drift length also linearly increases the drift resistance as given by the relation RDSW≈R□·LD where R□ is the sheet resistance of the implanted drift in ohms per square. Given that the specific on-resistance RDSA can be calculated by multiplying the transistor's resistivity RDSW times it's A/W packing density, the combining the two equations reveals for long drift devices
                                          R            DS                    ⁢          A                ≈                ⁢                              R            DS                    ⁢                      W            ·                          A              W                                                              =                ⁢                                            (                                                R                  s                                ⁢                                  L                  D                                            )                        ·                          (                              L                D                            )                                ∝                                    (                              L                D                            )                        2                              
and since LD≈BV/(Ecrit) then
                                          R            DS                    ⁢          A                ≈                ⁢                                            R              s                        ⁡                          (                              L                D                            )                                2                                        =                ⁢                                                            R                s                            ⁡                              (                                  BV                                      E                    crit                                                  )                                      2                    ∝                      BV            2                              
Thus the specific on-resistance of a lateral device increases in proportion to the square of the breakdown voltage because increasing the drift length of the lightly doped drain extensions both increases resistance of the transistor for a given gate width and also decreases the amount of gate width than can be packed into a given area.
So while low-voltage lateral MOSFETs can be made with low on-resistance, high-voltage lateral MOSFETs have a limited power handling capability. Metal resistance and high voltage reliability considerations further degrade the capability of lateral MOSFETs. Accordingly, while a lateral MOSFET can easily monitor current using a split-drain current mirror method, it is not very useful as a main power MOSFET.
Lateral MOSFET Reliability Limitations:
Implementing power MOSFETs as lateral devices in a planar process imposes certain limitations on device reliability. Specifically, planar devices exhibit their highest current densities and highest electric fields near the silicon surface when the device is in saturation, conducting current at large values of VDS. The combination of high electric fields and high current conduction leads to impact ionization and the formation of carriers accelerated to high velocities by localized electric fields.
These so called “hot” carriers, if injected into the nearby gate oxide can damage the dielectric and degrade the performance of the MOSFET, shift its threshold voltage, increase its on-state resistance and lower its transconductance. In some cases, it can short the gate entirely and kill the device. Such hot carrier-induced damage and especially hot electron injection or HEI-induced damage is virtually unavoidable in lateral MOSFETs formed at the silicon surface.
The problem becomes even worse at high voltages, where the conductivity of lightly-doped drain extensions can become modulated by impact ionization and pre-avalanche conditions. Impact ionization can also cause unwanted substrate currents and activate parasitic bipolar transistor action in the MOSFET, leading to voltage snapback and device destruction. This snapback problem in a device conducting current is known as a limitation in its “safe-operating-area”. Snapback in the off-state when the device is driven into avalanche is referred to as a limitation in the ruggedness of the device.
Regardless of whether the failure of the device is instantaneous in avalanche or in its safe-operating-area, or a gradual hot carrier-induced degradation, a lateral MOSFET's reliability and survivability can only be improved by limiting its current density, increasing its breakdown voltage, or limiting its maximum operating voltage. Unfortunately, running a device at a lower current density means the device must be oversized for its current rating, i.e. the device will be too big and too expensive a solution to be competitive in the marketplace. Increasing a lateral MOSFET's breakdown voltage adds series resistance to the device, again making the device too big and limiting it to non-power control circuit applications. And since many power applications operate at voltage above 5V, e.g. at 12V, 18V, 30V, 60V and even several hundred volts, limiting the device's maximum applied voltage is not an option.
Circuit Topology Limitations of Integrated MOSFETs;
The power circuit topology describes the physical relationship between the power source, the electrical load, and the power devices used to control the flow of energy in the load. Specifically, the power circuit topology determines which circuits can be integrated and which circuits must utilize discrete power MOSFETs.
FIG. 3 illustrates several common power circuit topologies using power MOSFETs as the semiconductor control element in the circuit or system. The MOSFETs are often referred to as “switches”, and the circuit topology as switch-load topology with the understanding that the definition of switch uses the broad IEEE definition as a device that “completes or breaks an electrical circuit”, without limiting whether the switch behaves digitally, resistively, or controls the magnitude of the current.
The three broadest topologies involve the high-side switch or high-side transistor, the low-side switch or low-side transistor, and the push-pull or half-bridge structure. Using MOSFETs, these topologies can also be referred to as a high-side MOSFET, a low-side MOSFET and push-pull MOSFETs. Topologically, two push-pull bridges can be used to construct an H-bridge or full bridge, while three or more push-pull outputs can be used to make a three-phase bridge or multi-phase bridge driver common for motor drive and high-power converters, regulators, and uninterrupted power supplies.
In a high-side switch or HSS topology as shown in FIGS. 3A and 3B, the electrical load 62 or 66 is connected to ground and the MOSFET is connected between the positive input Vbatt and the load. The load may comprise a resistive, capacitive, inductive, motor or transducer type device. Inductive loads include inductors or transformers comprising portions of switching power supplies or solenoids in electro-mechanical systems. Independent of the load type, no P-N diodes in the HSS topology become forward-biased, and they are therefore not represented schematically. If however, if load 62 is inductive, any interruption in its current will drive the voltage Vx below ground, forcing MOSFET 61 or 67 into avalanche breakdown in a condition known as unclamped inductive switching.
Without indicating how it is implemented, a current-sensing circuit for detecting the current I is preferably positioned on the high-side of MOSFET 61 or 67, where power from the battery input Vbatt enters the circuit. Ideally, the current-sensing circuitry can detect the current in normal load operation as well as in shorted load and avalanche current conditions. MOSFETs 61 and 67 in circuits 60 and 65 are P-channel and N-channel devices, respectively, and as shown each MOSFET includes a source-body short. Integration of N-channel MOSFET 67 requires a special process to isolate its source-body short from ground.
In a push-pull or half-bridge topology, as shown in FIGS. 3C and 3D, one side of an electrical load 73 or 78 is connected to a midpoint VX between a Vcc-connected high-side MOSFET 72 or 77 and a ground-connected low-side MOSFET 71 or 76. The load 73 or 78 may comprise a resistive, capacitive, or transducer type device. Inductive loads, solenoids and motors are given special treatment as illustrated in FIG. 3E. The side not connected to voltage Vx may be connected to ground, Vbatt, or another power source either directly of through another MOSFET or MOSFETs. A current-sensing circuit for detecting the current I is preferably positioned on the high-side, of MOSFETs 72 of 77, where power from the battery input Vbatt enters the circuit. In other cases, it may be desirable to monitor the current in loads 73 and 78 directly.
The high-side MOSFET 72 or 77 in push-pull circuits 70 and 75 is a P-channel or N-channel device, respectively, and as shown includes a source-body short. Integration of high side N-channel MOSFET 77 requires a special process to isolate its source-body shorted connection from ground. Low-side N-channel MOSFETs 71 and 76 do not, however, require any special fabrication process.
The circuit of FIG. 3E illustrates a push-pull circuit where the load 82 is inductive—a topology common to synchronous Buck switching voltage regulators. This circuit is also useful for loads such as motors and solenoids. Like circuits 70 and 75, low-side MOSFET 81 is an N-channel MOSFET while high-side MOSFET 83 is either an N-channel or a P-channel MOSFET. A current-sensing circuit for detecting the current I is preferably performed on the high-side of MOSFET 83, where power from the battery input Vbatt enters the circuit. In other cases it may be desirable to monitor the current in inductive load 82 directly or in the load which it powers. Because the Vx node drops below ground whenever current in high-side MOSFET 83 is interrupted, recirculation rectifier diode 84 connected in parallel with low-side MOSFET 84 is shown.
In a low-side switch or LSS topology, shown in FIG. 3F, the electrical load 86 is connected to the positive battery input Vbatt and an intermediate node Vx while MOSFET 87 is connected between the node Vx and ground. Load 86 may comprise a resistive, capacitive, or transducer type device. Inductive loads including inductors, transformers, solenoids and motors are given special consideration in FIG. 3G. Independent of the load type, no P-N diodes in the LSS topology become forward-biased, and they are therefore not represented schematically.
A current-sensing circuit for detecting the current I is generally positioned on the low-side of N-channel MOSFET 87. MOSFET 87 controls the flow of power into circuit 85 and requires no special process to implement its grounded source-body short. While theoretically current sensing could be performed anywhere in the series path of load 86 and MOSFET 87, low-side circuitry is simpler to implement since it is ground-referenced and does not float with the potential Vx.
FIG. 3G illustrates a LSS topology when load 91 is inductive, e.g., an inductor, solenoid, motor, or transformer. As shown, the voltage Vx is clamped by a clamping diode 92, a synchronous rectifier MOSFET 94, or both, which conduct whenever N-channel low-side MOSFET 93 interrupts the current flowing in inductive load 91 and the voltage Vx exceeds the voltage Vy across any capacitance 95. Topology 90 is common for boost and synchronous boost switching voltage regulators. Without clamping diode 92 or synchronous rectifier MOSFET 94, the voltage at Vx will rise without limit until low-side MOSFET 93 goes into avalanche breakdown during unclamped inductive switching.
A current-sensing circuit for detecting current I in circuit 90 is generally positioned on the low-side of MOSFET 93 and can detect the current in normal load operation as well as shorted-load and avalanche breakdown conditions. N-channel MOSFET 93 requires no special process to implement its grounded source-body short. If floating synchronous rectifier MOSFET 94 is a P-channel device, no special fabrication steps are required to implement a source body-short in the devices. Conversely, if MOSFET 94 is an N-channel device, an integrated source-body short requires electrical isolation to separate it from a surrounding P-type substrate.
In conclusion, the location of monitoring current in a circuit may vary depending on the topology of the circuit, i.e., relative positions of the load, the MOSFETs, and the power sources. Sensing the current in low-side N-channel MOSFETs, high-side P-channel MOSFETs, or floating P-channel synchronous rectifier MOSFETs requires no special fabrication steps using a CMOS process. Conversely, sensing current in high-side N-channel MOSFETs or in floating synchronous rectifier N-channel MOSFETs with integrated source-body shorts requires a more complex fabrication process to form electrical isolation. Since, without isolation, only P-channel MOSFETs may be used on the high-side, the power level achievable by integrated devices is limited to lower voltages and lower currents.
Current Sensing in Vertical DMOS:
One way to improving MOSFET reliability, performance and topological versatility is to employ vertical rather than lateral MOSFETs. In vertical MOSFETs, the current flows vertically from the top surface to the backside of the wafer, in a direction perpendicular to its surface. With vertical current flow MOSFETs, high current densities in high surface field regions are avoided.
The vertical MOSFETs 100 and 120, shown FIGS. 4A and 4B, are often referred to as DMOS devices, the “D” nomenclature referring to a double-diffused or dual-junction structure comprising a first body-to-drain junction contained within an epitaxial drain and a second source-to-body junction contained within a body region. In the N-channel vertical DMOS shown in FIGS. 4A and 4B, body regions 107 or 123, contacted by P+ implants 108 and 124, are diffused or implanted into a lightly-doped epitaxial layer 102 or 122 that is grown atop a heavily doped substrate 101 or 121. N+ source regions 109 and 125 are shorted to the body regions 107 or 123 by thick metal layers 110 and 128 and by optional barrier metal 110.
In the trenched DMOS device 100, a polysilicon gate 104 is embedded within a trench 105 etched into the silicon and lined with gate oxide 105; in the planar DMOS device 120, a polysilicon gate 127 is located above the surface of epitaxial layer 122 atop a gate oxide layer 126. The gate oxide layer 105 is protected from hot carrier injection by symmetrical body regions 107 on each side of trench 103 in trench MOSFET 100; the gate oxide layer 126 is protected from hot carrier injection by P-type body diffusions 123 that form a parasitic JFET structure beneath gate 127 and electrostatically shield gate oxide 126 in planar vertical MOSFET 120.
To achieve high-voltage operation in a vertical DMOS transistor, the thickness of the epitaxial layer must be increased and its doping concentration decreased, but the device's geometric cell density need be only moderately decreased. The on-resistance increase is therefore impacted only by the more resistive epitaxial layer. The specific on-resistance of the device is given byRDSA=BVn where including the impact of both the doping and thickness of the epitaxial layer, above 200V n≈2.5. Below 100V, the critical electric field of avalanche is also a factor of doping so that n≈1.0 and as a result the device's on-resistance depends more linearly on its breakdown voltage. So while vertical DMOS transistors exhibit a stronger dependence of on-resistance on breakdown voltage, their higher cell density A/W gives them superior performance over lateral MOSFETs with increasing voltage, especially at voltages over 20V.
A third variant of a vertical DMOS device, the super-junction DMOS illustrated in FIG. 4C exhibits a lower voltage dependence “n” but needs a slightly thicker epitaxial layer making it more useful at higher voltages, e.g. above 400V.
Shown in cross section, the super-junction DMOS 140 comprises a surface structure similar to that of a planar DMOS with a polysilicon gate 148 and gate oxide 149 overlapping a planar DMOS channel formed within a P-type body 144 and an N+ source region 145, both of which are formed within one or more of N-type epitaxial layers 142A-142F grown atop an N+ substrate 141. What differentiates super-junction DMOS 140 from conventional vertical DMOS 120 is its epitaxial layer, which rather than being all N-type material contains photomask-defined vertical columns 143 of P-type material, referred to as vertical charge control regions. P-type charge control columns 143 form a grid like pattern, separating the lightly-doped N-type epitaxial layer into vertical columns 142 of N-type material, having a surface geometry of stripes, rectangles, squares, or other closed polygonal shapes.
By limiting the total charge, i.e. the concentration times the column width, of both the P-type columns 143 and the N-type columns 142 to some maximum amount, the tradeoff between breakdown and on-resistance can be improved for high-voltage DMOS, especially above 400V. Using a principle similar to previously described lateral lightly doped drain MOSFETs, the P- and N-columns exhibit two-sided depletion spreading under reverse bias, and completely deplete before they reach the critical avalanche field and breakdown. The concentration of the N-type columns 142 does not matter so long that they fully deplete before the device reaches avalanche breakdown. Once fully depleted, the only electric field of importance is the vertical field between the P+ contact regions 146 and the N+ substrate 141. Similar to a P-I-N junction the vertical field is relatively constant, so the voltage varies linearly with vertical position within the P- or N-type columns. Because N-type columns 142 are fully depleted when DMOS device 140 is in its off state, the doping concentration of N-type columns 142 can be quite high, thereby reducing the resistance of the thick epitaxial drain when DMOS device 140 is conducting. The net benefit is a reduction in on-resistance in high breakdown voltage devices, so that in the relationship RDSA=BVn, the exponent n is reduced below that of a conventional DMOS, i.e. below 2.
The advantage of vertical DMOS devices 100, 120 and 140 is that they offer higher cell densities and greater ruggedness and reliability than lateral MOSFETs, especially since the gate oxide of a vertical DMOS is electrostatically shielded and not subject to hot carrier damage in saturation or in avalanche breakdown.
Current Sensing in Vertical DMOS;
Unfortunately all vertical DMOS cells, whether planar, trench-gated or super-junction, share a common drain and substrate. Because of their common drain construction, the aforementioned split drain current sensing method 22 or 42 cannot be integrated into a vertical DMOS transistor.
For example, a vertical trench-gated DMOS 200 of FIG. 5A is split into two devices with sources S1 and S2 and a common drain, wherein DMOS source S1 comprises a metal layer 203A, an N+ source region 205A, a P-body region 206A and a trench gate 204A and wherein DMOS source S2 comprises a metal layer 203B, an N+ source region 205B, a P-body region 206B and a trench gate 204B, all sharing a common drain comprising an N epitaxial layer 202 and an N+ substrate 201. The equivalent circuit diagram 220 in FIG. 5B reveals that the two MOSFETs 221A and 221B are connected as a common drain pair where the cathodes of body diodes 222A and 222B are common and only the anodes are separate.
It is extremely difficult to separately detect current in the two devices in this configuration. As shown in the low-side switch application 250 of FIG. 5C, trying to use a common-drain N-channel DMOS 251B to monitor current in a low resistance DMOS 251A requires a sense resistor 253, monitored by an amplifier 254, to be inserted between the source of DMOS 251B and ground. No resistor can be inserted into the grounded source of low resistance DMOS 251A without degrading its performance and increasing conduction losses. As a result, source voltage VS2 is no longer the same potential as grounded VS1, and a measurement error results. Not only does this condition force the two transistors to exhibit different values of VDS, but since they share a common gate bias VG, they each are biased to a different value of VGS further degrading their current matching, i.e. VGS1≠VGS2.
A similar scenario results in high-side monitoring circuit 270, shown in FIG. 5D, where a grounded sense resistor 273 in series with a sense DMOS 271B forces the voltage at VS2 to be different from the source follower output VS1 of power DMOS 271A. With differing gate-to-source and drain-to-source voltages, the mismatch in current can be severe. Attempts to force VS1 and VS2 to the same level are problematic, not only complicating the bias circuitry, but making the signal across sense resistor 273 too small for amplifier 274 to detect.
For the above reasons, the split-source vertical DMOS does not facilitate a useful current mirror. Sensitive to both VGS and VDS mismatches, the split source sense MOSFET is vastly inferior to and incompatible with the more normal split drain circuitry described previously. Unfortunately, the split drain device cannot be integrated into any vertical DMOS transistor, whether planar, trench or super-junction. These limitations, practically speaking, relegate all of today's vertical DMOS to the current sense resistor and VDS sensing methods for monitoring current. The problem is further exacerbated in high power devices.
Current Sensing in High Power Devices:
Unfortunately, vertical devices capable of delivering higher power to a load, especially those in high-voltage applications, comprise device structures and use technology not amenable to the aforementioned integrated current mirror and VDS sense current monitoring methods.
Such high power devices, including thyristors, gate turn-off thyristors or GTO's, insulated-gate bipolar transistors or IGBT's, utilize some mix of minority carrier and majority carrier current flow, making it virtually impossible to integrate the current sensing within the high power device. Specifically, minority carrier conduction easily shorts-out or bypasses any integrated sensing method. Devices with minority carrier conduction also exhibit non-linear or exponential current-voltage relationships extremely sensitive to temperature, non-uniform conduction, and hot spots.
For example, insulated gate bipolar transistor or IGBT 170, shown in FIG. 4D, has a cross section similar to that of vertical planar DMOS 120, shown in FIG. 4B, but utilizes a P-type substrate 171 instead of an N-type substrate. Holes are injected into a thick epitaxial layer 173 and collected by a deep P+ region 174 resulting in conductivity modulation of the epitaxial layer 173, reducing the drain resistance of the DMOS comprising an N+ source region 176, a P-type body region 175 and an N drain 173.
Thyristor 180 in FIG. 4E includes an N+ cathode 185, a P-type base 183 with a P+ contact region 184, a thick N-type epitaxial layer 182, and a P+ substrate anode 181. By forward-biasing cathode 185 to base terminals 187 and 186, injected electrons forward-bias the P-N junction between N-epitaxial layer 182 and P+ substrate 181, and the entire device latches into an on condition during which time N-epitaxial layer 182 becomes flooded with minority carriers. The main current must be diverted, i.e. commutated, to turn off the device. One variant, the gate turn off thyristor, or GTO, diverts the base current to provide some degree of gate control to shut the device off.
Measuring current in the P-N and P-I-N rectifier diodes 189, shown in FIG. 4F is also problematic, since minority carrier conduction occurs throughout a thick epitaxial layer 191, resulting in non-linear, temperature-sensitive conduction characteristics. As shown, P+ anode contact 194 and P-body region 192 injects holes into N− epitaxial layer 191, which recombine to form electron current in N+ substrate 190.
While Schottky diode 195, shown in FIG. 4G, does not exhibit significant minority carrier conduction, the diode's forward-bias characteristics of Schottky diode depend heavily on the built-in barrier potential between metal layer 198 and N-type epitaxial layer 197. Dividing anode 199 into segments does not insure that an accurate current reading can be made on only a fraction of the current into cathode 196. In all of the devices described above, only the resistor current-sensing method is applicable. But because the currents are high, the voltage drop across the resistor can cause increased power dissipation. Reducing the size of the resistor increases the sensitivity of the current-sensor to noise.
Summary of Current Sensing Techniques:
Table 1 compares the four common current sensing methods available today, namely the sense resistor, VDS sensing, the split-drain current mirror and the split-source current mirror or “sense FET” technique. The factors considered are summarized into sense methods, applicability of the technique to various devices, the operating conditions which the current sensing method applies, and certain circuit considerations.
As shown, the series sense resistor is most versatile but increases power losses by inserting a series resistance in the high current path. The resistor's power loss can be reduced by lowering the resistor's value, but this adversely results in a smaller signal and greater noise sensitivity. This tradeoff is a fundamental limitation of the otherwise versatile sense resistor method. With the caveat that the sense resistor is not integrated into the device being monitored, the sense resistor can sense current in virtually any device including discrete or integrated MOSFETs with lateral, vertical, DMOS, or super-junction implementations. It can also measure current in diodes or in devices with minority carrier conduction such as IGBT's and thyristors. Integrating the sense resistor into the device being measured is ill advised, limiting its accuracy by subjecting it to heating, package stress, and electrical noise. Moreover, silicon wafer fabrication does not produce precision resistors with high absolute accuracy, low temperature coefficients, or high current capability.
Referring again to Table 1, VDS sensing is much less accurate than using a precision sense resistor because it is sensitive to temperature, bias conditions, and noise and it is only applicable to MOSFETs operating in their linear operating region. VDS sensing does not work for devices with diode conduction, in avalanche, employing minority carrier conduction, or otherwise exhibiting non-linear current-voltage characteristics. To be applied to high-voltage applications, the VDS sensing circuitry requires an operational amplifier with a high voltage input capability.
The split-drain current mirror is good for monitoring the current in integrated lateral devices, but such devices are useful only for low voltage operation, primarily below 20V. It cannot be integrated into vertical devices. It is also not useful in diodes or devices exhibiting diode conduction, devices with minority carrier conduction, or operating in avalanche. To be applied to high-voltage applications, the split-drain current mirror sensing circuitry requires an operational amplifier with a high-voltage input capability.
The split-source current mirror or sense FET suffers numerous disadvantages compared to the split-drain current mirror, and it requires complex biasing to minimize the influence of source voltage biasing from causing both VDS and VGS mismatch error in its current measurement. Aside from its severe bias sensitivity, it also is subject to temperature variation, and noise, and incompatible with devices operating in avalanche breakdown, with diode conduction, or exhibiting minority carrier conduction. Its only real advantage is that it can be integrated into vertical DMOS devices, and with the aforementioned limitations, its use is practically limited to vertical DMOS discrete transistors operating below 100V.
TABLE 1Considera-SenseVDSCurrenttionResistorSensingMirrorSense FETSenseseriesparallelparallelparallelTopologyMethodmeasuremeasuresplit drainsplit sourceresistorRDS(on)mirrormirrorSeriestradeoffnoneNonenoneResistorvs. noiseDisc or ICeithereitherIC onlyVDMOSSwitchonlyTechanyMOSFETlateral, ICVDMOSApplicabilityonlyonlyonlyHV Effi-not Vnot Vpoorlimitedciencyspecificspecific(BV < 20 V)(BV < 100 V)Linear or Satbothlinear onlybothbetter in linearOpDiode OperyesnononoBipolar CondyesnononoOpAvalancheyesnononoOperNoise Sensitivetradeoffyesminimalyesvs. effi-ciencyBias SensitivenoextremelyminimalyesTemp SensitiveminimalextremelyminimalsomewhatIntegrate wpoor qualityoptionaloptionalnoPWMSense Biasnoneoff duringsimple bias Icomplex,CrktsatfloatingHV Op Ampnorequiredrequiredrequired
In conclusion, as shown in Table 1, no current sensing method available today is able to accurately measure current for the full range of available discrete and integrated power devices. What is needed is a current sense technique applicable for both integrated and discrete devices with minimal power dissipation and reduced noise and temperature sensitivity that does not require a high voltage input sense amplifier or unusual fabrication technology to implement.
Ideally the sensing method should be able to measure any combination of MOSFET current, forward-biased diode current, or avalanche current and should be compatible with majority carrier devices like MOSFETs and vertical DMOS or devices including minority carrier conduction such as IGBT's or thyristors.